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? 2013 microchip technology inc. ds25167b-page 1 mcp2561/2 features: ? supports 1 mb/s operation ? implements iso-11898-5 standard physical layer requirements ? very low standby current (5 a, typical) ?v io supply pin to interface directly to can controllers and microcontrollers with 1.8v to 5.5v i/o ? split output pin to stabilize common mode in biased split termination schemes ? can bus pins are disconnected when device is unpowered - an unpowered node or brown-out event will not load the can bus ? detection of ground fault: - permanent dominant detection on t xd - permanent dominant detection on bus ? power-on reset and voltage brown-out protection on v dd and v io pin ? protection against damage due to short-circuit conditions (positive or negative battery voltage) ? protection against high-voltage transients in automotive environments ? automatic thermal shutdown protection ? suitable for 12v and 24v systems ? meets or exceeds stringent automotive design requirements including ?hardware requirements for lin, can and flexray interfaces in automo- tive applications?, version 1.3, may 2012 ? high-noise immunity due to differential bus implementation ? high esd protection on canh and canl, meets iec61000-4-2 greater 8 kv ? available in pdip-8l, soic-8l and 3x3 dfn-8l ? temperature ranges: - extended (e): -40c to +125c - high (h): -40c to +150c description: the mcp2561/2 is a microchip technology inc. second generation high-speed can transceiver. it serves as an interface between a can protocol controller and the physical two-wire can bus. the device meets the automotive requirements for high-speed (up to 1 mb/s), low quiescent current, electromagnetic compatibility (emc) and electrostatic discharge (esd). package types mcp2561/2 family members MCP2562 pdip, soic v dd v ss r xd canh canl 1 2 3 4 8 7 6 5 v io stby t xd mcp2561 pdip, soic v dd v ss r xd canh canl 1 2 3 4 8 7 6 5 split stby t xd mcp2561 3x3 dfn* v dd v ss r xd canh canl 1 2 3 4 8 7 6 5 split stby t xd ep 9 MCP2562 3x3 dfn* v dd v ss r xd canh canl 1 2 3 4 8 7 6 5 v io stby t xd ep 9 * includes exposed thermal pad (ep); see ta b l e 1 - 2 device feature description mcp2561 split pin common mode stabilization MCP2562 v io pin internal level shifter on digital i/o pins note: for ordering information, see the ?product identification system? section on page 27. high-speed can transceiver
mcp2561/2 ds25167b-page 2 ? 2013 microchip technology inc. block diagram note 1: there is only one receiver implemented. the receiver can operate in low-power or high-speed mode. 2: only mcp2561 has the split pin. 3: only MCP2562 has the v io pin. in mcp2561, the supply for the digital i/o is internally connected to v dd . v dd canh canl t xd r xd driver and slope control thermal protection por uvlo digital i/o supply v io (3) v ss stby permanent dominant detect v io v io mode control v dd /2 split (2 ) wake-up filter canh canl canh canl receiver lp_rx (1) hs_rx
? 2013 microchip technology inc. ds25167b-page 3 mcp2561/2 1.0 device overview the mcp2561/2 is a high-speed can, fault-tolerant device that serves as the interface between a can protocol controller and the physical bus. the mcp2561/2 device provides differential transmit and receive capability for the can protocol controller, and is fully compatible with the iso-11898-5 standard. it will operate at speeds of up to 1 mb/s. typically, each node in a can system must have a device to convert the digital signals generated by a can controller to signals suitable for transmission over the bus cabling (differential output). it also provides a buffer between the can controller and the high-voltage spikes that can be generated on the can bus by outside sources. 1.1 mode control block the mcp2561/2 supports two modes of operation: ?normal ? standby these modes are summarized in tab l e 1 - 1 . 1.1.1 normal mode normal mode is selected by applying a low-level to the stby pin. the driver block is operational and can drive the bus pins. the slopes of the output signals on canh and canl are optimized to produce minimal electromagnetic emissions (eme). the high speed differential receiver is active. 1.1.2 standby mode the device may be placed in standby mode by applying a high-level to the stby pin. in standby mode, the transmitter and the high-speed part of the receiver are switched off to minimize power consumption. the low-power receiver and the wake-up filter block are enabled in order to monitor the bus for activity. the receive pin (r xd ) will show a delayed representation of the can bus, due to the wake-up filter. 1.2 transmitter function the can bus has two states: dominant and recessive. a dominant state occurs when the differential voltage between canh and canl is greater than v diff ( d )( i ). a recessive state occurs when the differential voltage is less than v diff ( r )( i ). the dominant and recessive states correspond to the low and high state of the t xd input pin, respectively. however, a dominant state initiated by another can node will override a recessive state on the can bus. 1.3 receiver function in normal mode, the r xd output pin reflects the differ- ential bus voltage between canh and canl. the low and high states of the r xd output pin correspond to the dominant and recessive states of the can bus, respectively. 1.4 internal protection canh and canl are protected against battery short- circuits and electrical transients that can occur on the can bus. this feature prevents destruction of the transmitter output stage during such a fault condition. the device is further protected from excessive current loading by thermal shutdown circuitry that disables the output drivers when the junction temperature exceeds a nominal limit of +175c. all other parts of the chip remain operational, and the chip temperature is low- ered due to the decreased power dissipation in the transmitter outputs. this protection is essential to protect against bus line short-circuit-induced damage. table 1-1: modes of operation mode stby pin r xd pin low high normal low bus is dominant bus is recessive standby high wake-up request is detected no wake-up request detected
mcp2561/2 ds25167b-page 4 ? 2013 microchip technology inc. 1.5 permanent dominant detection the mcp2561/2 device prevents two conditions: ? permanent dominant condition on t xd ? permanent dominant condition on the bus in normal mode, if the mcp2561/2 detects an extended low state on the t xd input, it will disable the canh and canl output drivers in order to prevent the corruption of data on the can bus. the drivers will remain disabled until t xd goes high. in standby mode, if the mcp2561/2 detects an extended dominant condition on the bus, it will set the r xd pin to recessive state. this allows the attached controller to go to low-power mode until the dominant issue is corrected. r xd is latched high until a recessive state is detected on the bus, and the wake-up function is enabled again. both conditions have a time-out of 1.25 ms (typical). this implies a maximum bit time of 69.44 s (14.4 khz), allowing up to 18 consecutive dominant bits on the bus. 1.6 power-on reset (por) and undervoltage detection the mcp2561/2 has undervoltage detection on both supply pins: v dd and v io . typical undervoltage thresh- olds are 1.2v for v io and 4v for v dd . when the device is powered on, canh and canl remain in a high-impedance state until both v dd and v io exceed their undervoltage levels. in addition, canh and canl will remain in a high-impedance state if t xd is low when both undervoltage thresholds are reached. canh and canl will become active only after t xd is asserted high. once powered on, canh and canl will enter a high-impedance state if the volt- age level at v dd or v io drop below the undervoltage levels, providing voltage brown-out protection during normal operation. in normal mode, the receiver output is forced to recessive state during an undervoltage condition. in standby mode, the low-power receiver is only enabled when both v dd and v io supply voltages rise above their respective undervoltage thresholds. once these threshold voltages are reached, the low-power receiver is no longer controlled by the por comparator and remains operational down to about 2.5v on the v dd supply (mcp2561/2). the MCP2562 transfers data to the r xd pin down to 1v on the v io supply. 1.7 pin descriptions table 1-2 describes the pinout. table 1-2: mcp2561/2 pinout mcp2561 3x3 dfn mcp2561 pdip, soic MCP2562 3x3 dfn MCP2562 pdip, soic symbol pin function 11 1 1t xd transmit data input 22 2 2v ss ground 33 3 3v dd supply voltage 44 4 4r xd receive data output 5 5 ? ? split common mode stabilization - mcp2561 only ?? 5 5v io digital i/o supply pin - MCP2562 only 6 6 6 6 canl can low-level voltage i/o 7 7 7 7 canh can high-level voltage i/o 8 8 8 8 stby standby mode input 9 ? 9 ? ep exposed thermal pad
? 2013 microchip technology inc. ds25167b-page 5 mcp2561/2 1.7.1 transmitter data input pin (t xd ) the can transceiver drives the differential output pins canh and canl according to t xd . it is usually connected to the transmitter data output of the can controller device. when t xd is low, canh and canl are in the dominant state. when t xd is high, canh and canl are in the recessive state, provided that another can node is not driving the can bus with a dominant state. t xd is connected to an internal pull-up resistor (nominal 33 k ? ) to v dd or v io , in the mcp2561 or MCP2562, respectively. 1.7.2 ground supply pin (v ss ) ground supply pin. 1.7.3 supply voltage pin (v dd ) positive supply voltage pin. supplies transmitter and receiver. 1.7.4 receiver data output pin (r xd ) r xd is a cmos-compatible output that drives high or low depending on the differential signals on the canh and canl pins, and is usually connected to the receiver data input of the can controller device. r xd is high when the can bus is recessive, and low in the dominant state. r xd is supplied by v dd or v io , in the mcp2561 or MCP2562, respectively. 1.7.5 split pin (mcp2561 only) reference voltage output (defined as v dd /2). the pin is only active in normal mode. in standby mode, or when v dd is off, split floats. 1.7.6 v io pin (MCP2562 only) supply for digital i/o pins. in the mcp2561, the supply for the digital i/o (t xd , r xd and stby) is internally connected to v dd . 1.7.7 can low pin (canl) the canl output drives the low side of the can differential bus. this pin is also tied internally to the receive input comparator. canl disconnects from the bus when mcp2561/2 is not powered. 1.7.8 can high pin (canh) the canh output drives the high-side of the can differential bus. this pin is also tied internally to the receive input comparator. canh disconnects from the bus when mcp2561/2 is not powered. 1.7.9 standby mode input pin (stby) this pin selects between normal or standby mode. in standby mode, the transmitter, high speed receiver and split are turned off, only the low power receiver and wake-up filter are active. stby is connected to an internal mos pull-up resistor to v dd or v io , in the mcp2561 or MCP2562, respectively. the value of the mos pull-up resistor depends on the supply voltage. typical values are 660 k ? for 5v, 1.1 m ? for 3.3v and 4.4 m ? for 1.8v 1.7.10 exposed thermal pad (ep) it is recommended to connect this pad to v ss to enhance electromagnetic immunity and thermal resistance.
mcp2561/2 ds25167b-page 6 ? 2013 microchip technology inc. 1.8 typical applications figure 1-1: mcp2561 with split pin figure 1-2: MCP2562 with v io pin 5v ldo v bat v dd v dd t xd r xd stby cantx canrx rbx v ss v ss pic mcp2561 split canh canl 4700 pf . 01f canh canl 60 60 300 ( optional 1 ) note 1: optional resistor to allow communication during bus failure (canl shorted to ground). 1.8v ldo v dd v dd t xd r xd stby cantx canrx rbx v ss vss pic MCP2562 canh canl 5v ldo v bat v io 0.1 f canh canl . 01f 120
? 2013 microchip technology inc. ds25167b-page 7 mcp2561/2 2.0 electrical characteristics 2.1 terms and definitions a number of terms are defined in iso-11898 that are used to describe the electrical characteristics of a can transceiver device. these terms and definitions are summarized in this section. 2.1.1 bus voltage v canl and v canh denote the voltages of the bus line wires canl and canh relative to ground of each individual can node. 2.1.2 common mode bus voltage range boundary voltage levels of v canl and v canh with respect to ground, for which proper operation will occur, if up to the maximum number of can nodes are connected to the bus. 2.1.3 differential internal capacitance, c diff (of a can node) capacitance seen between canl and canh during the recessive state, when the can node is disconnected from the bus (see figure 2-1 ). 2.1.4 differential internal resistance, r diff (of a can node) resistance seen between canl and canh during the recessive state when the can node is disconnected from the bus (see figure 2-1 ). 2.1.5 differential voltage, v diff (of can bus) differential voltage of the two-wire can bus, value v diff =v canh ?v canl . 2.1.6 internal capacitance, c in (of a can node) capacitance seen between canl (or canh) and ground during the recessive state, when the can node is disconnected from the bus (see figure 2-1 ). 2.1.7 internal resistance, r in (of a can node) resistance seen between canl (or canh) and ground during the recessive state, when the can node is disconnected from the bus (see figure 2-1 ). figure 2-1: physical layer definitions r in r in r diff c in c in c diff canl canh ground ecu
mcp2561/2 ds25167b-page 8 ? 2013 microchip technology inc. absolute maximum ratings? v dd ............................................................................................................................... ..............................................7.0v v io ............................................................................................................................... ...............................................7.0v dc voltage at t xd , r xd , stby and v ss .............................................................................................-0.3v to v io + 0.3v dc voltage at canh, canl and split ............................................................................................. ......... -58v to +58v transient voltage on canh, canl (iso-7637) ( figure 2-5 ) ................................................................... -150v to +100v storage temperature ............................................................................................................ ...................-55c to +150c operating ambient temperature .................................................................................................. ............-40c to +150c virtual junction temperature, t vj (iec60747-1) ....................................................................................-40c to +190c soldering temperature of leads (10 seconds) .................................................................................... ...................+300c esd protection on canh and canl pins for mcp2561 (iec 61000-4-2).............................................................14 kv esd protection on canh and canl pins for MCP2562 (iec 61000-4-2)...............................................................8 kv esd protection on canh and canl pins (iec 801; human body model)..............................................................8 kv esd protection on all other pins (iec 801; human body model)................................................................... ..........4 kv esd protection on all pins (iec 801; machine model) ............................................................................ ................300v esd protection on all pins (iec 801; charge device model) ...................................................................... ............750v ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
? 2013 microchip technology inc. ds25167b-page 9 mcp2561/2 2.2 dc characteristics electrical characteristics: extended (e): t amb = -40c to +125c and high (h): t amb = -40c to +150c; v dd = 4.5v to 5.5v, v io = 1.8v to 5.5v ( note 2 ), r l = 60 ? ; unless otherwise specified. characteristic sym min typ max units conditions supply v dd pin voltage range v dd 4.5 ? 5.5 supply current i dd ?510 ma recessive; v txd = v dd ? 45 70 dominant; v txd = 0v standby current i dds ?515 a mcp2561 ?515 MCP2562 ; includes i io high level of the por comparator v porh 3.8 ? 4.3 v low level of the por comparator v porl 3.4 ? 4.0 v hysteresis of por comparator v pord 0.3 ? 0.8 v v io pin digital supply voltage range v io 1.8 ? 5.5 v supply current on v io i io ?430 a recessive; v txd = v io ? 85 500 dominant; v txd = 0v standby current i dds ?0.3 1 a ( note 1 ) undervoltage detection on v io v uvd ( io ) ?1.2 ? v ( note 1 ) bus line (canh; canl) transmitter canh; canl: recessive bus output voltage v o ( r ) 2.0 0.5v dd 3.0 v v txd = v dd ; no load canh; canl: bus output voltage in standby v o ( s ) -0.1 0.0 +0.1 v stby = v txd =v dd ; no load recessive output current i o ( r ) -5 ? +5 ma -24v < v can < +24v canh: dominant output voltage v o ( d ) 2.75 3.50 4.50 v t xd = 0 canl: dominant output voltage 0.50 1.50 2.25 symmetry of dominant output voltage (v dd ? v canh ? v canl ) v o ( d )( m ) -400 0 +400 mv v txd = v ss dominant: differential output voltage v o ( diff ) 1.5 2.0 3.0 v v txd = v ss ; figure 2-2 , figure 2-4 recessive: differential output voltage -120 0 12 mv v txd = v dd , figure 2-2 , figure 2-4 -500 0 50 mv v txd = v dd , no load. figure 2-2 , figure 2-4 canh: short circuit output current i o ( sc ) -120 85 ? ma v txd = v ss ; v canh = 0v; canl: floating canl: short circuit output current ? 75 +120 v txd = v ss ; v canl = 18v; canh: floating note 1: only characterized; not 100% tested. 2: only MCP2562 has v io pin. for the mcp2561, v io is internally connected to v dd . 3: -12v to 12v is ensured by characterization, tested from -2v to 7v.
mcp2561/2 ds25167b-page 10 ? 2013 microchip technology inc. bus line (canh; canl) receiver recessive differential input voltage v diff ( r )( i ) -1.0 ? +0.5 v normal mode; -12v < v( canh , canl ) < +12v; see figure 2-6 ( note 3 ) -1.0 ? +0.4 standby mode; -12v < v( canh , canl ) < +12v; see figure 2-6 ( note 3 ) dominant differential input voltage v diff ( d )( i )0.9 ? v dd v normal mode; -12v < v( canh , canl ) < +12v; see figure 2-6 ( note 3 ) 1.0 ? v dd standby mode; -12v < v( canh , canl ) < +12v; see figure 2-6 ( note 3 ) differential receiver threshold v th ( diff ) 0.5 0.7 0.9 v normal mode; -12v < v( canh , canl ) < +12v; see figure 2-6 ( note 3 ) 0.4 ? 1.15 standby mode; -12v < v( canh , canl ) < +12v; see figure 2-6 ( note 3 ) differential input hysteresis v hys ( diff ) 50 ? 200 mv normal mode, see figure 2-6 , ( note 1 ) common mode input resistance r in 10 ? 30 k ? ( note 1 ) common mode resistance matching r in ( m )-1 0 +1%v canh = v canl , ( note 1 ) differential input resistance r in ( diff ) 10 ? 100 k ? ( note 1 ) common mode input capacitance c in ( cm )? ? 20 pfv txd = v dd ; ( note 1 ) differential input capacitance c in ( diff )? ? 10 v txd = v dd ; ( note 1 ) canh, canl: input leakage i li -5 ? +5 a v dd =v txd =v stby =0v. for MCP2562 , v io =0v. v canh = v canl = 5 v. common mode stabilization output (split) output voltage vo 0.3v dd 0.5v dd 0.7v dd v normal mode; i split = -500 a to +500 a 0.45v dd 0.5v dd 0.55v dd v normal mode; r l ? 1 m ? leakage current i l -5 ? +5 a standby mode; v split = -24v to + 24v (iso 11898: -12v ~ +12v) 2.2 dc characteristics (continued) electrical characteristics: extended (e): t amb = -40c to +125c and high (h): t amb = -40c to +150c; v dd = 4.5v to 5.5v, v io = 1.8v to 5.5v ( note 2 ), r l = 60 ? ; unless otherwise specified. characteristic sym min typ max units conditions note 1: only characterized; not 100% tested. 2: only MCP2562 has v io pin. for the mcp2561, v io is internally connected to v dd . 3: -12v to 12v is ensured by characterization, tested from -2v to 7v.
? 2013 microchip technology inc. ds25167b-page 11 mcp2561/2 digital input pins (t xd , stby) high-level input voltage v ih 0.7v io ?v io +0.3 v low-level input voltage v il -0.3 ? 0.3v io v high-level input current i ih -1 ? +1 a t xd : low-level input current i il( txd ) -270 -150 -30 a stby: low-level input current i il( stby ) -30 ? -1 a receive data (r xd ) output high-level output voltage v oh v dd - 0.4 ? ? v i oh = -2 ma ( mcp2561) ; typi- cal -4 ma v io - 0.4 ? ? i oh = -1 ma ( MCP2562) ; typi- cal -2 ma low-level output voltage v ol ??0.4vi ol = 4 ma; typical 8 ma thermal shutdown shutdown junction temperature t j( sd ) 165 175 185 c -12v < v( canh , canl ) < +12v, ( note 1 ) shutdown temperature hysteresis t j( hyst ) 20 ? 30 c -12v < v( canh , canl ) < +12v, ( note 1 ) 2.2 dc characteristics (continued) electrical characteristics: extended (e): t amb = -40c to +125c and high (h): t amb = -40c to +150c; v dd = 4.5v to 5.5v, v io = 1.8v to 5.5v ( note 2 ), r l = 60 ? ; unless otherwise specified. characteristic sym min typ max units conditions note 1: only characterized; not 100% tested. 2: only MCP2562 has v io pin. for the mcp2561, v io is internally connected to v dd . 3: -12v to 12v is ensured by characterization, tested from -2v to 7v.
mcp2561/2 ds25167b-page 12 ? 2013 microchip technology inc. figure 2-2: physical bit representation and simplified bias implementation canh, canl, split time canh canl split normal mode standby mode recessive recessive dominant split floating canl canh v dd /2 r xd v dd normal standby mode
? 2013 microchip technology inc. ds25167b-page 13 mcp2561/2 figure 2-3: test load conditions figure 2-4: test circuit for electrical characteristics 2.3 ac characteristics electrical characteristics: extended (e): t amb = -40c to +125c and high (h): t amb = -40c to +150c; v dd = 4.5v to 5.5v, v io = 1.8v to 5.5v ( note 2 ), r l = 60 ? ; unless otherwise specified. param. no. sym characteristic min typ max units conditions 1t bit bit time 1 ? 69.44 s 2f bit bit frequency 14.4 ? 1000 khz 3t txd - buson delay t xd low to bus dominant ? ? 70 ns 4t txd - busoff delay t xd high to bus recessive ? ? 125 ns 5t buson - rxd delay bus dominant to r xd ? ? 70 ns 6t busoff - rxd delay bus recessive to r xd ??110ns 7t txd - rxd propagation delay t xd to r xd ? ? 125 ns negative edge on t xd 8 ? ? 235 positive edge on t xd 9t fltr ( wake ) delay bus dominant to r xd (standby mode) 0.5 1 4 s standby mode 10 t wake delay standby to normal mode 5 25 40 s negative edge on stby 11 t pdt permanent dominant detect time ? 1.25 ? ms t xd = 0v 12 t pdtr permanent dominant timer reset ? 100 ? ns the shortest recessive pulse on t xd or can bus to reset permanent dominant timer v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all digital pins load co ndition 1 load co ndition 2 gnd r xd split t xd r l 100 pf 30 pf canh canl can transceiver 0.1 f v dd stby note: on MCP2562, v io is connected to v dd .
mcp2561/2 ds25167b-page 14 ? 2013 microchip technology inc. figure 2-5: test circuit for automotive transients figure 2-6: hysteresis of the receiver gnd r xd split t xd r l 500 pf 500 pf note: on MCP2562, v io is connected to v dd . canh canl can transceiver transient generator the wave forms of the applied transients shall be in accordance with iso-7637, part 1, test pulses 1, 2, 3a and 3b. stby v oh v ol 0.5 0.9 v diff (h)(i) v diff (v) r xd (receive data output voltage) v diff (r)(i) v diff (d)(i)
? 2013 microchip technology inc. ds25167b-page 15 mcp2561/2 2.4 timing diagrams and specifications figure 2-7: timing diag ram for ac characteristics figure 2-8: timing diagram for wakeup from standby figure 2-9: permanent dominant timer reset detect 3 7 4 8 0v v dd t xd (transmit data input voltage) v diff (canh, canl differential voltage) r xd (receive data output voltage) 5 6 v txd = v dd 10 0v v dd v stby v canh /v canl input voltage 0 v dd /2 11 12 t xd v diff (v canh -v canl ) driver is off minimum pulse width until can bus goes to dominant after the falling edge
mcp2561/2 ds25167b-page 16 ? 2013 microchip technology inc. 2.5 thermal specifications parameter symbol min typ max units test conditions temperature ranges specified temperature range t a -40 ? +125 ? c -40 ? +150 operating temperature range t a -40 ? +150 ? c storage temperature range t a -65 ? +155 ? c thermal package resistances thermal resistance, 8l-dfn 3x3 ? ja ?56.7? ? c/w thermal resistance, 8l-pdip ? ja ?89.3? ? c/w thermal resistance, 8l-soic ? ja ? 149.5 ? ? c/w
? 2013 microchip technology inc. ds25167b-page 17 mcp2561/2 3.0 packaging information 3.1 package marking information 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e example: 8-lead dfn (3x3 mm) 8-lead pdip (300 mil) example: xxxxxxxx xxxxxnnn yyww mcp2561 e/p ^^256 1307 3 e part number code mcp2561-e/mf dadr mcp2561t-e/mf dadr mcp2561-h/mf dads mcp2561t-h/mf dads MCP2562-e/mf dadu MCP2562t-e/mf dadu MCP2562-h/mf dadt MCP2562t-h/mf dadt dadr 1307 256 nnn mcp2561e sn ^^1246 256 3 e or mcp2561h sn ^^1246 256 3 e or mcp2561 h/p ^^256 1307 3 e
mcp2561/2 ds25167b-page 18 ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2013 microchip technology inc. ds25167b-page 19 mcp2561/2 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp2561/2 ds25167b-page 20 ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2013 microchip technology inc. ds25167b-page 21 mcp2561/2 n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c
mcp2561/2 ds25167b-page 22 ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2013 microchip technology inc. ds25167b-page 23 mcp2561/2 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp2561/2 ds25167b-page 24 ? 2013 microchip technology inc.
? 2013 microchip technology inc. ds25167b-page 25 mcp2561/2 appendix a: revision history revision b (march 2013) ? updated the ?mcp2561/2 family members? table on page 1. revision a (march 2013) ? original release of this document.
mcp2561/2 ds25167b-page 26 ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. ds25167b-page 27 mcp2561/2 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. -x /xx package temperature range device device: mcp2561: high-speed can transceiver with split mcp2561t: high-speed can transceiver with split (tape and reel) (dfn and soic only) MCP2562: high-speed can transceiver with v io MCP2562t: high-speed can transceiver with v io (tape and reel) (dfn and soic only) temperature range: e = -40c to +125c (extended) h = -40c to +150c (high) package: mf = plastic dual flat, no lead package - 3x3x0.9 mm body, 8-lead p = plastic dual in-line - 300 mil body, 8-lead sn = plastic small outline - narrow, 3.90 mm body, 8-lead examples: a) mcp2561-e/mf: extended temperature, 8ld 3x3 dfn package. b) mcp2561t-e/mf: tape and reel, extended temperature, 8ld 3x3 dfn package. c) mcp2561-e/p: extended temperature, 8ld pdip package. d) mcp2561-e/sn: extended temperature, 8ld soic package. e) mcp2561t-e/sn: tape and reel, extended temperature, 8ld soic package. a) mcp2561-h/mf: high temperature, 8ld 3x3 dfn package. b) mcp2561t-h/mf: tape and reel, high temperature, 8ld 3x3 dfn package. c) mcp2561-h/p: high temperature, 8ld pdip package. d) mcp2561-h/sn: high temperature, 8ld soic package. e) mcp2561t-h/sn:tape and reel, high temperature, 8ld soic package.
mcp2561/2 ds25167b-page 28 ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. ds25167b-page 29 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62077-091-7 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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